The present invention relates to means for improving the range of response to low-amplitude input signals of a dynamic frequency divider circuit used as a primary frequency divider circuit in an electronic timepiece, being coupled to directly receive a standard frequency signal which is generated by a standard frequency signal source such as a quartz crystal oscillator circuit of the electronic timepiece. The present invention enables the range of response to be optimized with respect to a particular supply voltage applied to power the dynamic frequency divider circuit and the standard frequency signal source, so that these can be operated at a supply voltage which is substantially lower than the timepiece battery voltage with a very low amplitude signal being output from the standard frequency signal source, and in addition can enable the response characteristics of the dynamic frequency divider circuit to be made substantially independent of variations in the timepiece battery voltage, to thereby enable dependable operation of the dynamic frequency divider circuit with a very low amplitude of standard frequency signal.
At the present time, the great majority of electronic timepieces being manufactured utilize a quartz crystal oscillator circuit as a standard frequency signal source for producing an output signal which is frequency divided to provide a unit time signal, having a frequency of, for example, 1 Hz. This unit time signal is applied to drive a stepping motor, in the case of an analog display type of timepiece, or is input to timekeeping counter circuits which drive a digital display through driver/decoder circuits, in the case of a digital timepiece. In recent years, there has been an increasing requirement for a reduction of the power consumption of such electronic timepieces. Since CMOS field-effect transistor integrated circuits are almost universally used, the main cause of circuit power consumption lies in the standard frequency signal source, i.e. the quartz crystal oscillator circuit, and in the primary stages of frequency division which are coupled to the output signal from the quartz crystal oscillator circuit, since these circuits all operate at a high switching speed. In order to reduce the power consumption of these circuits, therefore, measures are taken such as reducing the value of supply voltage applied thereto to a lower level than the battery output voltage, and reducing the amplification factor of the amplifier used in the quartz crystal oscillator circuit. However, these measures also result in a reduction in the amplitude of output signal produced by the quartz crystal oscillator circuit, and in some cases the peak-to-peak amplitude of this signal may become as low as 1/2 of the battery voltage of the timepiece. Such a low amplitude of input signal applied to the primary frequency divider circuit stages may result in incorrect operation of these stages. This is particularly true in the case of a dynamic frequency divider circuit being used as a primary frequency divider circuit. A dynamic frequency divider circuit is often used as a primary frequency divider circuit when the frequency of oscillation of the timepiece quartz crystal oscillator circuit is made very high, e.g. of the order of several MHz, in order to obtain the advantages of superior timekeeping accuracy obtainable by using a high frequency quartz crystal vibrator as a frequency standard. Thus, in the prior art, it has been difficult to obtain the advantages of utilizing a high frequency quartz crystal oscillator circuit as a standard frequency signal source together with the advantages of low power consumption which can be obtained by operating the quartz crystal oscillator circuit and primary frequency divider circuit stages at a low value of supply voltage, with a very low signal level being input to the primary frequency divider circuit stages from the quartz crystal oscillator circuit.
With the present invention, as will be described hereinafter, the above disadvantages encountered in the prior art are substantially reduced, thereby making practicable an electronic timepiece having a high frequency quartz crystal oscillator circuit as a standard frequency signal source but in which the level of power consumption in the quartz crystal oscillator circuit and in the primary frequency divider circuit stages is held to a very low level, and in which reliable timekeeping operation is assured in spite of variations in the timepiece battery voltage.